YouDDR
High Speed DDR Interface Solution
YouDDR Advanced Technology
Brite provides a complete DDR subsystem including not only controller, PHY and IO, but also corresponding tuning and configuration software. And this solution can support LPDDR2, DDR3, LPDDR3, DDR4 and LPDDR4/4x combo PHY with the data rate from 667Mbps to 4266Mbps. YouPHY-DDR delivers a combination of DDR high speed and low power performance. With dynamic self-calibrating logic (DSCL) and dynamic adaptive bit calibration (DABC) technology, YouDDR can automatically compensate chip/package/board/memory PVT variation and bit-bit skew. YouDDR delivers higher DDR performance, smaller area and shorter time-to-market.
YouDDR Subsystem
Key DDR Subsystem Features
Highly flexible and customizable DFI 4.0 compliant DDR controller architecture
Supports up to 32 target interfaces including AXI, AHB and FIFO-based interfaces
User-customizable arbiter (scheduler)
Supports multi-rank DRAM variation compensation
Comprehensive DDR protocol training
- CA training
- DQ read training
- DQ write training
- Write leveling
- Vref training
PHY is DFI 4.0 compatible and backwards-compatible to earlier DFI standards for simplified integration with existing
- DFI-compliant Controllers
PHY includes DSCL technology
- Automatically compensates for DDR interface timing due to static (process-related) variations and dynamic variations due to operating temperature, voltage, and data patterns
PHY includes DABC technology
- Automatically compensates for bit-bit skew within each byte lane
DSCL delivers lowest PHY latency of 0.5 – 1 clock cycles
Fast and simple system bring-up via DSCL hardware routine
ATC(Auto Tracking and Compensation) technology
- DLL's ATC
- Round-Trip's ATC
- Read-DQ-Eye's ATC
Improved long term system reliability
Flexible, rectilinear PHY layout offers industry’s smallest PHY area and is hardened to match IO pad frame
PHY (and optionally IO) configured as drop-in hard macro for easy implementation
Combo PHY options include:
- DDR2/DDR3 PHY Combo
- LPDDR2/DDR3 PHY Combo
- LPDDR2/LPDDR3/DDR3 PHY Combo
- DDR3/DDR4 PHY Combo
- LPDDR34/DDR34 PHY Combo
- LPDDR3/4 + DDR4 PHY Combo
- LPDDR34(x)/DDR4 PHY Combo
- DDR4 PHY
High performance, low jitter DDR IO
Low power / small footprint
Silicon proven
The DDR controller is delivered as RTL while the PHY and IO are delivered as hardened macros to fit the target chip floorplan and padframe. Brite can deliver a fully hardened DDR subsystem （controller, PHY and IO） if requested.
Netlist, SDF, LEF, LIB, Verilog, timing reports, technical documentation.
Brite provides complete layout and integration guidelines for the DDR IP and a technical review of the DDR subsystem implementation prior to tapeout. Support is also available for silicon bring up.
LPDDR4-4266Eye-Diagram
